PIC16C621A-04I/P【PDF 7/89 页】IC MCU OTP 1KX14 COMP 18DIP

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AT90S1200

0838H–AVR–03/02

Figure 17. Watchdog Reset during Operation

Interrupt Handling

The AT90S1200 has two Interrupt Mask Control Registers: the GIMSK (General Inter-

rupt Mask Register) at I/O space address $3B and the TIMSK (Timer/Counter Interrupt

Mask Register) at I/O address $39.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-

bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag

bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared

(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the

flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared

(zero), the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for

as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

General Interrupt Mask

Register – GIMSK

Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S1200 and always reads as zero.

Bit

$3B

INT0

GIMSK

Read/Write

R/W

Initial Value

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